Technical Field
The disclosure relates in general to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device with complete profile.
Description of the Related Art
Size of semiconductor device has been decreased for these years. Reduction of feature size, improvements of the rate, the efficiency, the density and the cost per integrated circuit unit are the important goals in the semiconductor technology. The electrical properties of the device have to be maintained even improved with the decrease of the size, to meet the requirements of the commercial products in applications. For example, the layers and components with damages, which have considerable effects on the electrical properties, would be one of the important issues of the device for the manufacturers. Generally, a semiconductor device with good electrical performance requires the gates with excellent properties such as complete profiles and sufficient height.
The current trench-filling process, such as contact metal forming process, generally suffers from the erosion and recesses due to too many times of planarization and cleaning steps (such as CMP). FIG. 1A-FIG. 1D illustrate a conventional method for forming contact metal; for example, forming the conductive plugs or metal gates in the FinFET device. After the trenches are formed in the insulation (such as the integration of the spacers S, the contact etch stop layer CESL and the interlayer dielectric ILD) on the substrate 10 (FIG. 1A), the barrier layer 11, the seed layer 13S and the bulk layer 13B are consequently formed as shown in FIG. 1B. Afterward, upper portions of the bulk layer 13B, the seed layer 13S and the barrier layer 11 are removed by more than one CMP polishing process; however, this would cause erosion and recesses of the structure, which leads to gate height loss, as shown in FIG. 1C. Also, a cleaning treatment such as CMP buffering would lead to further loss of the gate height, and cause the dishing profile, as shown in FIG. 1D. It is known that the structure of FIG. 1D manufactured by the conventional method has undesirable effect on the electrical characteristics of the device.
Accordingly, it is desired to develop a method for forming a conductor (such as gate or contact plug) with sufficient height and also provide a complete profile without flaws of erosion and/or dishing.